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Introduction to Digital Systems: Modeling, Synthesis, and Simulation Using VHDL
book

Introduction to Digital Systems: Modeling, Synthesis, and Simulation Using VHDL

by Mohammed Ferdjallah
July 2011
Intermediate to advanced content levelIntermediate to advanced
225 pages
6h 22m
English
Wiley
Content preview from Introduction to Digital Systems: Modeling, Synthesis, and Simulation Using VHDL

6.5 THREE-VARIABLE KARNAUGH MAP

Karnaugh maps can be modified to handle a greater number of inputs. For example, combining two two-variable maps together can create a three-variable Karnaugh map. Figure 6.4 shows a three-variable truth table and a three-variable Karnaugh map. Here x1 and x2 identify the rows of the map and x3 identifies the columns. To assure that all the minterms in the adjacent cells of the map can be combined into a single product term, the adjacent cells must differ by only one bit position. As you may notice, the values of x1 and x2 count in the order 00, 01, 11, 10 rather than the usual 00, 01, 10, 11. This ensures that each cell varies by only one bit position from each adjacent cell. The map also wraps around itself, so the top and bottom cells are also adjacent to each other. The cell adjacency of a Karnaugh map obeys the Gray code, which consists of a sequence of code where each value differs by only one bit position at a time.

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Figure 6.4 Three-Variable Karnaugh Map

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Figure 6.5 Karnaugh Map Simplification of a Three-Variable Logic Function

In a three-variable map it is possible to combine cells to produce product terms that correspond to a single cell, two adjacent cells, or a group of four adjacent cells. An example of this case is shown in Figure 6.5

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ISBN: 9780470900550Purchase book