Introduction to Digital Systems: Modeling, Synthesis, and Simulation Using VHDL

7.6 DECODERS

A decoder is a multiple-input, multiple-output logic circuit that converts coded inputs into coded outputs, where the input and output codes are different. The input code generally has fewer bits than the output code, and there is one-to-one mapping from input code words into output code words. The general structure of a decoder circuit is shown in Figure 7.16. The enable inputs, if present, must be asserted for the decoder to perform its normal mapping function. The most commonly used input code is an N-bit binary code, where an N-bit word represents one of 2^N different coded values. Normally, they range from 0 through 2^N − 1. The input code lines select which output is active. The remaining output lines are disabled. Thus, the decoder is intended to provide a binary code to other circuits, such as a memory circuit. In this case, the decoder is referred to as an address decoder because it selects one address of a memory location. However, a decoder could also be used to channel a stream of data on a designated output line selected by the input code lines.

Figure 7.16 Block Diagram of a N : 2^N Decoder

Figure 7.17 Logic Implementation of a 2 : 4 Decoder

A 2: 4 decoder is illustrated in Figure 7.17. The two data inputs are x₁ and x₂. These inputs represent a 2-bit binary ...