Processor Description Languages

6.4 Functional Verification 151

0

1234

5

10

15

20

25

30

35

Pipeline Stages

Clock Frequency (MHz) Area (K gates)

FIGURE 6.13

Pipeline stage exploration.

Addition of operations

Fig. 6.14 presents exploration results for addition of opcodes using three processor

configurations.The three configurations are shown in Fig. 6.14. The first configura-

tion has four parallel execution units: FU1, FU2, FU3, and FU4. The FU1 supports

three operations: ⫹, ⫺, and ⫻. The FU2, FU3, and FU4 support (⫹, ⫺, ⫻), (and,

or), and (sin, cos), respectively. The second configuration is obtained by adding a

cos operation in the FU3 of the first configuration. This generated reduction of

schedule ...