Processor Description Languages

324 CHAPTER 12 MAML

12.4.5 Architecture Synthesis for Rapid Prototyping

As mentioned in Section 12.4.2,a highly parameterizable template written in VHDL

is used during the back-end design phase of a weakly programmable processor array.

The template parameters on the array level are,for instance,array size,configuration

memory size, possible interconnect topologies, etc. On the PE level, the number

and size of input and output ports, number of functional units, size of instruction

memory, and local register file can be specified for each PE individually. All these

parameters are taken directly from the MAML architecture description.

To obtain some initial ...