Processor Description Languages

4.3 A Structural Skeleton of the Processor 69

Connections such as buses and nets (wires) fall in the class of transitory storage

elements, which are defined in nML to pass a value from input to output without

delay. Transitories are declared with the keyword

trn. Pipeline registers, declared

with the keyword

pipe,are a special kind of transitory storage having a delay of one

cycle. These are used to describe multi-stage actions. Some examples from tctcore:

trn A<num>; // ALU input

trn B<num>; // ALU input

trn C<num>; // ALU output

trn XD<num>; // X data bus

pipe F<acc>; // pipeline between multiply and accumulate

It is not needed to declare all nets and