Processor Description Languages

4.5 Pipeline Hazards: Stalls and Bypasses 81

when a register is written in a late stage while a next instr uction reads that

register in an early stage.

■ Control hazards occur when jump instructions change the program counter.

A processor pipeline consists of an instruction fetch pipeline,that is,the instruc-

tion fetch stage (

IF) optionally preceded by one or more prefetch stages, and an

execution pipeline,starting with the instruction decode stage (

ID) and one or more

execute stages, which may include memory access and write-back stages.

In nML, the execution pipeline is explicitly modeled in the action attributes,

while the instruction fetch pipeline ...