Processor Description Languages

12.2 Description of Single Processor Architectures 305

Example 12.4

Definition of functional units.

<Unit name="ADDER" number="1" stages="1">

<Unitopset>

<Opname name="add" />

<Opname name="sub" />

<Read1 bankname="regA" />

<Read1 bankname="regB" />

<Read2 bankname="regA" />

<Read2 bankname="regB" />

<Write bankname="regB" />

</Unitopset>

</Unit>

<Unit name="MULT" number="1" stages="2">

<Unitopset>

<Opname name="mul" />

<Read1 bankname="regA" />

<Read2 bankname="regB" />

<Write bankname="regA" />

</Unitopset>

</Unit>

In Example 12.4, two functional units are described. The ADDER performs its

defined operations in one execution stage,whereas the

MULT operates in two