book

Processor Description Languages

by Prabhat Mishra, Nikil Dutt

July 2011

Intermediate to advanced

432 pages

14h 36m

English

Morgan Kaufmann

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Front Cover
Processor Description Languages Applications
Copyright Page
Table of Contents (1/2)
Table of Contents (2/2)
List of Contributors (1/2)
List of Contributors (2/2)
Preface
About the Editors
Chapter 1. Introduction to Architecture Description Languages

1.1 What is an Architecture Description Language?
1.2 ADLs and Other Languages
1.3 Classification of Contemporary ADLs
1.3.1 Content-based Classification of ADLs
1.3.2 Objective-based Classification of ADLs
1.4 ADLs: Past, Present, and Future
1.5 Book Organization
References
Chapter 2. ADL-driven Methodologies for Design Automation of Embedded Processors
2.1 Design Space Exploration
2.2 Retargetable Compiler Generation
2.2.1 Retargetability Based on ADL Content
2.2.2 Retargetability Based on Compiler Phases
2.2.3 Retargetability Based on Architectural Abstractions
2.3 Retargetable Simulator Generation
2.3.1 Interpretive Simulation
2.3.2 Compiled Simulation2.3.3 Mixed Approaches
2.4 Architecture Synthesis
2.4.1 Implementation Generation Using Processor Templates
2.4.2 ADL-driven Implementation Generation
2.5 Top-Down Validation
2.5.1 Validation of ADL Specification
2.5.2 Implementation Validation
2.6 Conclusions
References
Chapter 3. MIMOLA—A Fully Synthesizable Language
3.1 Introduction3.1.1 Origin of the Language
3.1.2 Purpose of the Language
3.1.3 Related Work: State of the Art in the Early Years
3.1.4 Outline of This Chapter
3.2 Salient Features of the Mimola Language3.2.1 Overall Structure of Description3.2.2 Declarations, Data Types, and Operations
3.2.3 Program Definition
3.2.4 Structure Definition
3.2.5 Linking Behavior and Structure
3.2.6 Putting Things Together
3.3 Tools and Results3.3.1 Design Flow3.3.2 The Front-end and Internal Design Representations
3.3.3 Mapping to Register Transfers
3.3.4 Simulation
3.3.5 Architectural Synthesis
3.3.6 Test Program Generation
3.3.7 Code Generation
3.3.8 Overall View of the Dependence among MSS Tools
3.3.9 Designs Using MSS2
3.4 Conclusions
3.4.1 Evolution of Ideas and Directions3.4.2 What Went Wrong and What Went Right
3.4.3 Summary
References
Chapter 4. nML: A Structural Processor Modeling Language for Retargetable Compilation and ASIP Design
4.1 Introduction
4.2 The nML Processor Description Formalism
4.3 A Structural Skeleton of the Processor
4.3.1 Memories and Registers
4.3.2 Storage Aliases
4.3.3 Transitory Storage
4.3.4 Immediate Constants and Enumeration Types
4.3.5 Functional Units
4.4 Instruction-Set Grammar
4.4.1 Breaking Down the Instruction Set: AND Rules and OR Rules
4.4.2 The Grammar Attributes
4.4.3 Synthesized Attributes
4.4.4 Action Attribute
4.4.5 Image Attribute
4.4.6 Syntax Attribute
4.4.7 Mode Rules and Value Attributes
4.4.8 Inherited Attributes
4.5 Pipeline Hazards: Stalls and Bypasses
4.5.1 Control Hazards
4.5.2 Structural and Data Hazards
4.6 The Evolution of nML
4.7 A Retargetable Tool Suite for ASIPs
4.7.1 Chess: A Retargetable C Compiler
4.7.2 Checkers: A Retargetable Instruction-set Simulator Generator
4.7.3 Go: A Hardware Description Language Generator4.7.4 Risk: A Retargetable Test-program Generator4.7.5 Broad Architectural Scope
4.8 Design Examples
4.8.1 Portable Audio and Hearing Instruments4.8.2 Wireline Modems
4.8.3 Wireless Modems
4.8.4 Video Coding4.8.5 Network Processing
4.9 Conclusions
References
Chapter 5. LISA: A Uniform ADL for Embedded Processor Modeling, Implementation, and Software Toolsuite Generation
5.1 Language-based ASIP Modeling
5.1.1 Intuitive Modeling Idea5.1.2 ISA Modeling
5.1.3 Structure Modeling: Base Processor
5.1.4 Levels of Abstraction in LISA
5.1.5 LISA-based Processor Design
5.2 Automatic Software Toolsuite Generation
5.2.1 Instruction-set Simulator
5.2.2 The Compiler Designer
5.2.3 Custom Instruction Synthesis for LISA-based Processor Design
5.2.4 Instruction Opcode Synthesis
5.3 Automatic Optimized Processor Implementation
5.3.1 Automatic Generation of RTL Processor Description
5.3.2 Area and Timing-driven Optimizations
5.3.3 Energy-driven Optimizations
5.3.4 Automatic Generation of JTAG Interface and Debug Mechanism
5.4 Processor Verification
5.4.1 Equivalence Check via Simulation
5.4.2 Generation of Test Vectors from LISA Descriptions for Instruction-set Verification
5.5 System-Level Integration
5.5.1 Retargetable Processor Integration
5.5.2 Multiprocessor Simulation
5.6 Compact Modeling of Advanced Architectures
5.6.1 VLIW Architecture Modeling
5.6.2 Partially Reconfigurable Processor Modeling
5.7 Case Study
5.7.1 ASIP Development for Retinex-like Image and Video Processing
5.7.2 Retargetable Compiler Optimization for SIMD Instructions
5.8 Conclusions
References
Chapter 6. Expression: An ADL for Software Toolkit Generation, Exploration, and Validation of Programmable SOC Architectures
6.1 Expression ADL
6.1.1 Structure
6.1.2 Behavior
6.2 Software Toolkit Generation and Exploration
6.2.1 Retargetable Compiler Generation
6.2.2 Retargetable Simulator Generation
6.2.3 Design Space Exploration
6.3 Architecture Synthesis for Rapid Prototyping
6.3.1 Synthesizable HDL Generation
6.3.2 Rapid Prototyping and Exploration
6.4 Functional Verification
6.4.1 Specification Validation
6.4.2 Test Generation Using Model Checking
6.4.3 Implementation Validation
6.5 Conclusions
References
Chapter 7. ASIP Meister
7.1 Overview of ASIP Meister
7.1.1 Framework Overview
7.1.2 Features
7.1.3 A Short History
7.1.4 ASIP Meister Usage in Academia7.2 Architecture Model
7.3 ADL in ASIP Meister
7.3.1 Overview of ADL Structure
7.3.2 Specification Entry Using GUI
7.3.3 Microoperation Description
7.3.4 VLIW Extension
7.4 Generation of HDL Description
7.4.1 DFG Construction from Microoperation Description
7.4.2 Pipeline Registers and Datapath Selectors Insertion
7.5 Case Study
7.5.1 MIPS and DLX
7.5.2 M32R
7.5.3 MeP
7.6 Conclusion
7.7 Acknowledgments
References
Chapter 8. TIE: An ADL for Designing Application-specific Instruction Set Extensions
8.1 Introduction8.1.1 Adapting the Processor to the Application
8.1.2 Tensilica Instruction Extension Language and Compiler
8.2 Design Methodology and Tools8.2.1 Designing Application-specific Instructions
8.2.2 Design Automation with the TIE Compiler
8.3 Basics of Tie Language
8.3.1 A basic TIE Acceleration Example
8.3.2 Defining a Basic TIE Instruction
8.3.3 Instruction Encodings
8.3.4 Instruction Datapath
8.4 Adding Processor State
8.4.1 Defining a State Register
8.4.2 Defining a Register File
8.4.3 Data Type and Compiler Support
8.4.4 Data Parallelism and SIMD
8.5 Vliw Machine Design
8.5.1 Defining a VLIW Instruction
8.5.2 Hardware Cost of VLIW
8.6 Language Constructs for Efficient Hardware Implementation8.6.1 Sharing Hardware between Instructions
8.6.2 TIE Functions
8.6.3 Defining Multicycle Instructions
8.7 Custom Data Interfaces
8.7.1 Import Wire and Export State
8.7.2 TIE Queue
8.7.3 TIE Lookup
8.8 Hardware Verification
8.8.1 Microarchitectural Verification
8.9 Case Study of An Audio DSP Design
8.9.1 Architecture and ISA Overview
8.9.2 Implementation and Performance
8.10 Conclusions
References
Chapter 9. MADL—An ADL Based on a Formal and Flexible Concurrency Model
9.1 Introduction
9.2 Operation State Machine Model
9.2.1 Static OSM Model
9.2.2 Dynamic OSM Model
9.2.3 Scheduling of the OSM Model
9.3 MADL
9.3.1 The AND-OR Graph: A Review
9.3.2 The Core Layer
9.3.3 The Annotation Layer
9.4 Support for Tools
9.4.1 Cycle Accurate Simulator (CAS)
9.4.2 Instruction Set Simulator
9.4.3 Disassembler9.4.4 Register Allocator
9.4.5 Instruction Scheduler
9.5 Results
9.6 Related Work
9.7 Conclusion
References
Chapter 10. ADL++: Object-Oriented Specification of Complicated Instruction Sets and Microarchitectures
10.1 Flexible Architecture Simulation Toolset (FAST)
10.1.1 Overview of the Toolset
10.2 The FAST/ADL Model
10.2.1 Timing of Events
10.2.2 Time Annotated Actions and Parallelism in the Microarchitecture
10.2.3 Microarchitecture Specification
10.2.4 ISA Specification
10.2.5 Putting It Together
10.3 Review of Complex Instruction Set Architectures
10.3.1 Variable Length Instructions
10.3.2 Many Memory Addressing Modes
10.3.3 Overlapping Registers
10.3.4 Mixed Arguments
10.3.5 Assembly Language Syntax
10.4 Sets and Regular Expressions as Language Constructs
10.4.1 Registers and Their Specification Using Sets
10.4.2 Regular Expressions and Addressing Modes
10.5 Instruction Templates and Multiple Conditional Inheritance
10.5.1 Inheritance with a Twist: Multiple Conditional Inheritance
10.5.2 Instruction Template
10.6 Object-Oriented Microarchitecture Specification
10.6.1 Artifacts as Objects
10.6.2 Deriving Complex Architectures From Objects
10.7 Epilogue10.8 History of Fast and ADL++
References
Chapter 11. Processor Design with ArchC
11.1 Overview
11.2 Syntax and Semantics (1/2)
11.2 Syntax and Semantics (2/2)
11.3 Integration Through a TLM Interface
11.3.1 ArchC TLM Interfaces and Protocol
11.3.2 TLM Interrupt Port
11.3.3 A Word on ArchC Simulators
11.4 A Multicore Platform Example
11.5 Conclusions
References
Chapter 12. MAML: An ADL for Designing Single and Multiprocessor Architectures
12.1 History of MAML
12.2 Description of Single Processor Architectures
12.2.1 Syntax
12.2.2 Example of a VLIW Processor Architecture
12.3 Description of Multiprocessors
12.3.1 Related Work
12.3.2 Description of Parallel Processing Elements
12.3.3 Parametric Domains as a Description Paradigm
12.3.4 Description of Adaptive Interconnect Topologies
12.3.5 Case Study of a Tightly Coupled Processor Arrays
12.4 Approaches and Tools Around MAML
12.4.1 Application Mapping
12.4.2 Design Framework
12.4.3 Interactive Visual Architecture Entry
12.4.4 Simulator Generation
12.4.5 Architecture Synthesis for Rapid Prototyping
12.5 Conclusions and Future Work
12.6 Acknowledgments
References
Chapter 13. GNR: A Formal Language for Specification, Compilation, and Synthesis of Custom Embedded Processors
13.1 Introduction
13.2 Overview of NISC Technology
13.3 Modeling NISC Architectures and Systems
13.3.1 GNR Formalism
13.3.2 GNR Rules
13.3.3 GNR Syntax
13.3.4 Basic Components
13.3.5 Hierarchical Components
13.3.6 Modeling an NISC Architecture
13.3.7 Communication Modeling
13.3.8 Generating RTL Code from GNR
13.4 Experiments: Design-Space Exploration Using NISC and GNR
13.4.1 Designing General-purpose NISCs
13.4.2 Custom Datapath Design for DCT (1/2)
13.4.2 Custom Datapath Design for DCT (2/2)
13.4.3 Communicating NISC Components
13.5 Conclusion
References
13.6 Index Terms
Chapter 14. HMDES, ISDL, and Other Contemporary ADLs
14.1 HMDES14.1.1 HMDES Language
14.1.2 Structural Overview of Machine Description (1/2)
14.1.2 Structural Overview of Machine Description (2/2)
14.1.3 Trimaran Infrastructure
14.2 ISDL
14.2.1 ISDL Language
14.2.2 ISDL-driven Methodologies
14.3 RADL
14.4 SIM-nML
14.5 UDL/I
14.6 Flexware14.7 Valen-C
14.8 TDL
14.9 Conclusions
References
Index (1/2)
Index (2/2)

Content preview from Processor Description Languages

196 CHAPTER 8 TIE

Table 8.3 Load store memory interface signals.

Name Width Direction Purpose

Vaddr 32 Out

Load/store address

MemDataIn

{128,64,32,16,8}

128,64,32,16,8 In Load data

MemDataOut

{128,64,32,16,8}

128,64,32,16,8 Out Store data

LoadByteDisable 16 Out Byte disable signal

StoreByteDisable 16 Out Byte disable signal

8.4.3 Data Type and Compiler Support

The TIE compiler automatically creates a new data type for every register ﬁle deﬁned

by the TIE designer. The data type has the same name as the register ﬁle, and is

available for use as the “type” of a variable in C/C++ programs. The Xtensa C/C++

compiler understands that variables of this type reside ...

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Communication Architectures for Systems-on-Chip

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ISBN: 9780123742872

Cloud Computing

Data Engineering

Data Science

AI & ML

Programming Languages

Software Architecture

IT/Ops

Security

Design

Business

Soft Skills

Processor Description Languages

by Prabhat Mishra, Nikil Dutt

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