Processor Description Languages

122 CHAPTER 5 LISA: A Uniform ADL for Embedded Processor

OPERATION alu_op<id> IN pipe.DC

{

DECLARE

{

GROUP opcode= { add<id> || sub<id> || and<id> };

GROUP src1 = { reg || dreg };

INSTANCE bypass_src1<id>, bypass_src2<id>, alu_op_ex<id>;

}

CODING { 0b0 opcode 0b00000 src1 src2 dst }

SYNTAX { opcode ~" " dst"," src1 "," src2 }

BEHAVIOR

{

bypass_src1();

bypass_src2();

}

ACTIVATION { alu_op_ex }

}

FIGURE 5.15

Template-based operation description for VLIW.

an operation with definite identifier value, as will be done typically for a functional

unit residing into one slot being activated by different instructions from different

slots.

5.6.2 Partially Reconfigurable Processor ...