Processor Description Languages

80 CHAPTER 4 nML

opn store_ind_instr (m : ind_mem_acc, r : reg_sel)

{

action : stage EX1..EX2: m`EX2` = XD`EX1` = r`EX1`;

syntax:m"="r","m.1;

image : "1"::r::m;

}

The OR mode ind_mem_acc passes along the attributes of its alternatives, and

both the value and action attributes are instantiated by the parameter

m in the

action attribute of the load rule

load_ind_instr and store rule store_ind_instr.

Note the timing specification for the memory access in the value attribute of

mode

ind_mem_acc1. Tctcore is assumed to have synchronous data memories with

timing specification as follows. The address is applied in stage

EX1,while the mem-

ory core access happens in