Processor Description Languages

8.8 Hardware Verification 211

value matches the expected value of the result. This is done over a number of test

vectors that cover all the corner case values and several typical values. Simulation

of the application code using the TIE instrinsics is also part of this verification.

The control logic that integrates the new instructions into the Xtensa processor

is automatically generated by the TIE compiler. This includes instruction decode

logic, pipelining controls such as data hazard prevention and data forwarding, and

appropriate interfaces to the instruction fetch and load-store units of the proces-

sor. The designer is not responsible for verifying ...