Processor Description Languages

10.3 Review of Complex Instruction Set Architectures 263

Registers ECX,EDX,and EBX are broken down in a similar fashion. Register s ESP,

EBP, ESI, and EDI have aliases for the lower 16 bits SP, BP, SI,and DI, respectively. As

a side note,while the earlier stated eight registers are noted as general purpose,the

registers occasionally have special uses, hence the seemingly obtuse names of the

registers. The special uses are shown in Fig. 10.10(b).

10.3.4 Mixed Arguments

Unlike RISC architectures, instructions in CISC architectures can operate directly

on memory. That is, RISC machines, or load-store architectures, have only two

instructions that can