July 2011
Intermediate to advanced
432 pages
14h 36m
English
Content preview from Processor Description Languages
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320 CHAPTER 12 MAML
FIGURE 12.16
Designing a parallel processor array implementing an edge detection application using Design
Framework.
is used to instantiate a weakly programmable processor ar ray implementation with
the given architectural parameters.
12.4.3 Interactive Visual Architecture Entry
On the left-hand side of Fig. 12.16, the architecture design area is shown where
the user can observe the entire processor array with all processing elements sur-
rounded by their interconnect wrappers. The designer can switch the design area
to a mode showing the interconnection network between the processor elements.
On the right-hand side of Fig. 12.16,
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