October 2018
Intermediate to advanced
555 pages
17h 33m
English
Content preview from Principles of Synchronous Digital Hierarchy
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498 Principles of Synchronous Digital Hierarchy
of 64 consecutive frames, this byte generates a 64-byte TTI signal. These 64
frames are repeated four times in a multiframe of 256 frames as mentioned
in Section 16.7.1. The rst 16 frames, i.e., 0 to 15, contain the SAPI, the next 16
frames, i.e., 16 to 31, contain the DAPI, and the rest of the frames, i.e., 32 to 63,
contain information that is specic to the operator.
The second byte of SM (9th byte of OTU frame) contains the bit interleaved
parity (BIP-8) for error check (for details of BIP check, see Section 6.7).
The third byte of SM (10th byte of OTU frame) contains a backward error
indica ...
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