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Principles of Synchronous Digital Hierarchy
book

Principles of Synchronous Digital Hierarchy

by Rajesh Kumar Jain
October 2018
Intermediate to advanced
555 pages
17h 33m
English
CRC Press
Content preview from Principles of Synchronous Digital Hierarchy
294 Principles of Synchronous Digital Hierarchy
interpreted and stored. The average frequency of the incoming clock is com-
pared with that of the local clock. If both the clocks have the same average
frequency, no change in the pointer value is carried out. However, if there is
a difference in the clock frequencies of the recovered clock with respect to
the local clock, the pointer value is changed. The new pointer is then inserted
into the VC-4, SOH is added, and the STM-1 is retransmitted, all using local
clock. The pointer adjustment procedure and the role of H1, H2, and H3
bytes are as follows.
The H3 bytes generally contain
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Publisher Resources

ISBN: 9781466517271