Principles of Synchronous Digital Hierarchy

123Signal Impairments, Error Detection, and Correction

gets added to the signal because during these timing adjustments,

the phase can never be matched perfectly in the practical systems

as explained in (i) above. We will see in subsequent chapters on ple-

siochronous digital hierarchy (PDH) and synchronous digital hier-

archy (SDH) that for equalizing the bit rates of E1 tributaries before

multiplexing, additional bits are introduced in the tributaries. When

these bits are removed at the demultiplexing stage, the clock has to

have irregularity to some extent because some bits that were intro-

duced as stuff bits for equalizing the bit rates of all tributaries are

required to be removed. This irregularity of the clock for dropping

the stuff