Digital Systems: Principles and Design

231Binary Arithmetic and Decoding and Mux Logic Units

Example 10.19 will give a logic design of 8 of 1 Mux using three 4 of 1 Muxs. Example

10.20 will give a logic design and implementation using a multiplexer for F = P M(1, 7, 9,

13) (Implementation of POS Boolen expression).

Point to Remember

A multiplexer with one-line output is also a Boolean expression implementer and imple-

ments of a SOP (or POS cells) Karnaugh map. The literal variables are the inputs to the

channel selector lines and minterm (or mux-term) selectors are given at the input lines of

a multiplexer.

A three-variable expression and its Karnaugh map can also be implemented by a