Digital Systems: Principles and Design

181Open Collector, Open Drain and Tristate Gates

20 mA is treated as logic 1, if V

p

= 12 V, we can then treat state 1 for V » of 12 V

instead and use the taletype coil in place of R

p

.

2. An enhanced current sources from a TTL gate output .

3. Both i

source

and i

sink

are now controlled externally. Fan-out to the connected stages

can now be as per requirement. We can draw about 10000 mA i.e. 10 mA through an

LED whatever may be the TTL family. (We can use a higher power LED also by

keeping V

p

= 12 V and choosing R

L

appropriately.) Now, LED glow indicates the

logic states.

4. Increased noise margin is present.

5. A higher gate speed is obtained if we work ...