October 2006
Intermediate to advanced
544 pages
20h 23m
English
Content preview from Digital Systems: Principles and Design
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281Implementation of Combinational Logic by Standard ICs and Programmable ROM Memories
TABLE 12.2
Address inputs Outputs Present link numbers
A 2 A1 A 0 F 3 F 2F 1F 0 OR3 OR2 OR1 OOR0
0 0 0 1 1 0 1 25 17 1
0 0 1 0 0 1 1 10 2
Table 12.2 Contd.
4 INPUT VARIABLES
F
3
F
2
F
1
F
0
´ Programmable links
m(15)
m(14)
m(13)
m(12)
m(11)
m(10)
m(9)
m(8)
m(7)
m(6)
m(5)
m(4)
m(3)
m(2)
m(1)
m(0)
A
3
A
3
A
2
A
2
A
1
A
1
A
0
A
0
A
3
A
3
A
2
A
2
A
1
A
1
A
0
A
0
64 48 32 16
63 47 31 15
62 46 30 14
61 45 29 13
60 44 28 12
59 43 27 11
58 42 26 10
57 41 25 9
56 40 24 8
55 39 23 7
54 38 22 6
53 37 21 5
52 36 20 4
51 35 19 3
50 34 18 2
49 33 17 1
..16
49......64 33......48 17......32 1....
OR
3
OR
2
OR
1
OR
0
LINK Numbers
1to64
(a)
FIGURE 12.13 (a) 64 fusible ...
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