Digital Systems: Principles and Design

509CPLDs and FPGAs

FIGURE 21.1 (a) Output stage cell of a PAL (b) Output stage cell of a registered PAL (c) Macrocell of a GAL.

21.2 REGISTERED PAL

Many a times, the output bit (s) needs to be stable like in a memory cell and is according to

the inputs at the instance of a clock edge or clock pulse (master-slave) transition. For ex-

ample, refer Figure 16.2(a) sequential logic circuit for a PIPO register. In that circuit an X

i

1 product term

as out enable

7 product

terms

1/0–m'

1/0–m'

1/0–m'

Feedback inputs for AND arrays

PAL

(a)

DQ

Q

Out enable to all

tristate NOTs

7 or 8 product

terms

Clock to

all sDFF

Output =

D

m'

at

clock edge

Feedback inputs for the AND arrays

(b) ...