October 2006
Intermediate to advanced
544 pages
20h 23m
English
Content preview from Digital Systems: Principles and Design
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298
Digital Systems
13.3 PLA (PROGRAMMABLE LOGIC ARRAYS)
Each AND array corresponds to a SOP minterm or implicant. The output of each AND array
is given to an m-input OR. An output of OR corresponds to output, Y.
(1) In general, there should be (2.n) input 2
n
number AND gates with OR gate for each
output variable, Y. However, in actual practice, these are limited as there are limited
numbers of AND gates used in the PLAs.
(2) Similarly in general, there should be a 2
n
input OR gate at each output variable, Y.
However, in actual practice, these are limited as there are limited numbers l of AND
gates used in the PLAs and therefore there are (l/m) input ...
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