Digital Systems: Principles and Design

385Sequential Circuits for Registers and Counters

on a clock transition. It gives parallel outputs, which are the same as the next state. Par-

allel inputs mean D

i

= X

i

and parallel outputs mean Y

i

= Q

i

where i = 0, 1, 2 or 3 for a 4-

bit PIPO. Note: i = 0, 1, 2... n  1 for an n-bit register.

16.1.3 Number of Bits in a Register

Figure 16.2(a) shows a PIPO buffer register. Example 16.3 will explain the circuit of the

buffer register.

16.2 SHIFT REGISTERS

Figure 16.2(b) shows the circuit of a serial in serial out (SISO) shift register. Figure 16.2(c)

gives the different forms of the shift registers. A set of cascaded flip-flops to store the infor-

mation ...