October 2006
Intermediate to advanced
544 pages
20h 23m
English
Content preview from Digital Systems: Principles and Design
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402
Digital Systems
FIGURE 16.13 (a) Clearing all Qs (b) Presetting all Qs (c) Setting and clearing of Qs using the JAM inputs (d) Synchronous
clear, preset and load.
input transition i.e. activation (net time taken > t
s
+ DT
FF
). Here, the DT
FF
is propagation de-
lay within a FF of the counter.
16.8 TIMING DIAGRAMS
Figures 16.14, 16.15, 16.16 and 16.17 show the timing diagrams in a SISO, in a left-shift
shift SIPO register, in a ripple counter and in a synchronous counter, respectively.
FF
.
.
.
.
.
Q
FF
Q
CLR
CLR
Clear
input
FF
.
.
.
.
.
Q
FF
Q
Present
input
PR
PR
FF
.
.
.
.
.
Q
PR
X
0
FF
Q
PR
X
3
(a) (b) (c)
Q
0
Q
n
D
CLK
n
CLK
0
PR
CLR
PR
Q
Q
0
Q
n
D
0
CLR
CLK
n
CLK
0
CLR
PR
PR
.
.
.
Q
0
Q
0
D
0
X
0
CLK
0
D
n
X
n
.
.
.
Q
Q
Q
CLK
n
(d)
CLEAR ...
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