Digital Systems: Principles and Design

243Binary Arithmetic and Decoding and Mux Logic Units

FIGURE 10.23

A

1

A

0

I

3

– I

0

I

19

– I

16

F

0

F

4

F

1

F

5

I

7

– I

4

I

23

– I

20

I

11

– I

8

I

27

– I

24

F

2

F

6

F

3

F

7

I

15

– I

12

I

31

– I

28

I

15

– I

0

F

0

F

1

F

2

F

3

F

4

F

5

F

6

F

7

A

3

A

2

A

3

A

2

I

31

– I

16

A

4

0

F

I

31

– I

0

Give a logic design and implementation using the multiplexers for F

1

= S m(3, 7, 9, 10) and

F

2

is S m(2, 7, 12, 15).

Solution

Multiplexer is Boolean expression implementer when the inputs are given at the channel

selector pins and the inputs are used also as a minterm generator for F

1

give inputs X3, X7,

X9 and X10 = 1, other inputs as 0s. Apply the four inputs at the channel select input pins. For

F

2

, make X2, X7, X12 and X15 as 1 and apply inputs at the ...