Digital Systems: Principles and Design

335Sequential Logic, Latches and Flip-Flops

14.8 CLOCK INPUTS

14.8.1 Level Clocking of a Clock Input

Recall the circuit of Figure 14.4(a), called a level clocking circuit. Whenever CLK becomes

1 then only the circuit is transparent (responds) to the R and S inputs.

Level clocking circuit has the following difficulties:

(i) Often the input state or states are not permitted to change at the clock state

 or at the

clock state ¯ or at the clock state 1. All changes at the inputs S and R must be over

when the clock input is in logic state 0.

(ii) Assume that level 1 activates the clock input. Time interval during which CLK = 1

and CLK undergoes 1 to 0 transition ...