1.What are the steps followed when to formulate the problem when designing a com-
binational circuit?
2.Given two Boolean expressions, what are the steps followed to implement it with
minimum number of NOR gates.
3.Given two Boolean expressions what are the steps followed to implement it with
minimum number of NAND gates.
4.Given two Boolean expressions what are the steps followed to implement it with
minimum delays at each level.
5.How do you equalize the delays due to the different number of literal terms in a
Boolean expression?
6.Why do we design TTL circuits by the NANDs as building block and CMOS
circuits with ...
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