Digital Systems: Principles and Design

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Digital Systems

A typical CMOS logic circuit dissipates 2.5 mW static, 600 mW/MHz. What is the average

power dissipation assuming maximum operational frequency of 10 MHz? What will be the

power dissipated at 500 kHz operation?

1. At 100 MHz, the power dissipation will be (2.5 mW + 6000 mW). Average

dissipation assuming 50% time static and 50% maximum rate operation = 3001.5

mW.

2. Since power dissipation is 600 mW/MHz, at 500 kHz, it will be half. It means

300 mW.

What are the correct characteristics among the DTL, ECL, CMOS and TTL gates? (A) or

(B) or (C) or (D) [A GATE (2003) Competition Examination Question].

(A) Minimum Fan-out DTL, ...