Digital Systems: Principles and Design

355Sequential Circuits Analysis, State Minimization, State Assignment and Circuit Implementation

Figure 15.3(a) shows using two D flip flops a clocked sequential circuit-3 in which the

final stage combinational circuit output Y depends on the Q as per Moore model. Following

are the inputs, present states, outputs, input functions and output function of circuit-3:

Output Y is taken from AND gate having inputs from the between Q

1

and Q

2

of the FFs.

Input D

2

is from an AND gate having inputs X and Q

1

. Input D

1

is from the AND-OR

array implementing (X.

Q

2

.

Q

1

+

X

.

Q

2

.Q

1

).

15.4.2 Classification of a Sequential

Circuit as Mealy Model Circuit

Recall the sequential ...