book

Digital Systems: Principles and Design

Name: Digital Systems: Principles and Design
Author: Raj Kamal
ISBN: 9788131707081

by Raj Kamal

October 2006

Intermediate to advanced

544 pages

20h 23m

English

Pearson India

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DIGITAL SYSTEMS: Principles and Design
Copyright
Dedication
Contents (1/2)
Contents (2/2)
Preface
Acknowledgements
Chapter 1: Basic Digital Concepts
1.1 Concepts of ' 1 's, '0's
1.2 Analog vs. Digital Circuits
EXAMPLES

EXERCISES
QUESTIONS
Chapter 2: Number Systems
2.1 DECIMAL NUMBER
2.2 BINARY NUMBER
2.3 USE OF BINARY NUMBERS TO REPRESENT A NUMBER
2.4 USE OF OCTAL NUMBERS TO REPRESENT A NUMBER
2.5 USE OF DECIMAL NUMBERS TO REPRESENT A NUMBER
2.6 USE OF HEXADECIMAL NUMBERS TO REPRESENT A NUMBER
2.7 USE OF BCD NUMBER TO REPRESENT A DECIMAL NUMBER
2.8 FRACTIONAL NUMBERS
EXAMPLES (1/2)
EXAMPLES (2/2)
EXERCISES
QUESTIONS
Chapter 3: Binary Arithmetic and Two's Complement Arithmetic
3.1 BINARY ADDITION ARITHMETIC
3.2 ARITHMETIC NUMBER REPRESENTATIONS
3.3 BINARY SUBTRACTION
3.4 BINARY MULTIPLICATION OF UNSIGNED NUMBERS
3.5 MULTIPLICATION METHOD WHEN MULTIPLIER IS 2n WHERE n IS AN INTEGER
3.6 MULTIPLICATION METHOD WHEN MULTIPLIER IS A SMALL NUMBER
3.7 MULTIPLICATION METHOD FOR n-BIT BY N-BIT SIGNED NUMBERS, X AND Y3.8 BINARY ARITHMETIC DIVISION BY SUCCESSIVE SUBTRACTION METHOD
EXAMPLES (1/2)
EXAMPLES (2/2)
EXERCISES
QUESTIONS
Chapter 4: Boolean Algebra and Theorems, Minterms and Maxterms
4.1 THE NOT, AND, OR LOGIC OPERATIONS
4.2 THE NAND AND NOR LOGIC OPERATIONS
4.3 THE XOR, NOT-XOR, NOT-NOT LOGIC OPERATIONS
4.4 BOOLEAN ALGEBRAIC RULES (FOR OUTPUTS FROM THE INPUTS)
4.5 BOOLEAN ALGEBRAIC LAWS
4.6 DEMORGAN THEOREMS
4.7 THE SUM OF THE PRODUCTS (SOPs) AS PER BOOLEAN EXPRESSION AND MINTERMS
4.8 PRODUCT OF THE SUMS AND MAXTERMS FOR A BOOLEAN EXPRESSION
EXAMPLES (1/2)
EXAMPLES (2/2)
EXERCISES
QUESTIONS
Chapter 5: Karnaugh Map and Minimization Procedures
5.1 THE THREE-VARIABLE KARNAUGH MAP AND TABLES
5.2 FOUR VARIABLE KARNAUGH MAP AND TABLES
5.3 FIVE AND SIX VARIABLE KARNAUGH MAPS AND TABLES
5.4 AN IMPORTANT FEATURE IN THE DESIGN OF A KARNAUGH MAP
5.5 SIMPLIFICATION OF LOGIC CIRCUIT REALIZATION BY MINIMIZATION USING ADJACENCIES
5.6 DRAWING OF LOGIC CIRCUIT USING AND-OR GATES, OR-AND GATES, NAND'S ONLY, NOR'S ONLY
5.7 REPRESENTATIONS OF A FUNCTION (COVER) FOR A COMPUTER-AIDED MINIMIZATION FOR SIMPLIFYING THE LOGIC CIRCUITS (1/2)
5.7 REPRESENTATIONS OF A FUNCTION (COVER) FOR A COMPUTER-AIDED MINIMIZATION FOR SIMPLIFYING THE LOGIC CIRCUITS (2/2)
5.8 MULTI-OUTPUT SIMPLIFICATION
5.9 TWO OUTPUTS SIMPLIFICATION—COMPUTER-BASED PRIME IMPLICANTS USING STAR PRODUCT AND SHARP OPERATIONS
5.10 COMPUTER-BASED MINIMIZATION—QUINE-McCLUSKEY METHOD
EXAMPLES (1/2)
EXAMPLES (2/2)
EXERCISES
QUESTIONS
Chapter 6: Logic Gates
6.1 REVISION OF THE IMPORTANT GATES
6.2 DIODE CIRCUIT
6.3 BIPOLAR JUNCTION TRANSISTORS AND MOSFETS
6.4 RTL, DTL, TTL LOGIC GATES (1/2)
6.4 RTL, DTL, TTL LOGIC GATES (2/2)
6.5 EMITTER COUPLED LOGIC (ECL)
6.6 INTEGRATED INJECTION LOGIC (I2L)
6.7 HIGH THRESHOLD LOGIC (HTL)
6.8 NMOS
6.9 CMOS
6.10 MEANINGS OF SPEED, PROPAGATION DELAY, OPERATING FREQUENCY, POWER DISSIPATED PER GATE, SUPPLY VOLTAGE LEVELS, OPERATIONAL VOLTAGE LEVELS THAT DEFINE LOGIC STATES 1 AND 0
6.11 SPEED, PROPAGATION DELAY, OPERATING FREQUENCY, POWER DISSIPATED PER GATE, SUPPLY VOLTAGE LEVELS, OPERATIONAL VOLTAGE LEVELS THAT DEFINE LOGIC STATES ' 1 ' AND '0' FOR VARIOUS FAMILIES OF GATES
EXAMPLES (1/2)
EXAMPLES (2/2)
EXERCISES
QUESTIONS
Chapter 7: Interfacing Circuits between the Logic Gates of Same Family, Different Families and Types
7.1 REVISION OF THE IMPORTANT TOPICS
7.2 CONSIDERATIONS FOR INTERCONNECTIONS AND INTERFACING
7.3 INTERFACING CMOS AND TTL GATES
7.4 INTERFACING CMOS WITH CMOS GATES
EXAMPLES
EXERCISES
QUESTIONS
Chapter 8: Open Collector, Open Drain and Tristate Gates
8.1 OPEN COLLECTOR GATE
8.2 OPEN DRAIN GATE
8.3 QUASI BIDIRECTIONAL GATE
8.4 TRISTATE GATE
EXAMPLES
EXERCISES
QUESTIONS
Chapter 9: Problem Formulation and Design of the Combinational Circuits
9.1 COMBINATIONAL CIRCUIT
9.2 PROBLEM FORMULATION IN A COMBINATIONAL CIRCUIT
9.3 DESIGN OF A COMBINATIONAL CIRCUIT
EXAMPLES (1/3)
EXAMPLES (2/3)
EXAMPLES (3/3)
EXERCISES
QUESTIONS
Chapter 10: Binary Arithmetic and Decoding and Mux Logic Units
10.1 BINARY ARITHMETIC UNITS
10.2 DECODER
10.3 ENCODER
10.4 MULTIPLEXER
10.5 DEMULTIPLEXER
EXAMPLES (1/3)
EXAMPLES (2/3)
EXAMPLES (3/3)
EXERCISES
QUESTIONS
Chapter 11: Code Converters, Comparators and Other Logic Processing Circuits
11.1 CODE CONVERTERS
11.2 EQUALITY AND MAGNITUDE COMPARATORS BETWEEN TWO FOUR-BIT NUMBERS
11.3 ODD PARITY AND EVEN PARITY GENERATORS
11.4 THE 4-BIT AND, OR, XOR BETWEEN TWO WORDS
EXAMPLES (1/2)
EXAMPLES (2/2)
EXERCISES
QUESTIONS
Chapter 12: Implementation of Combinational Logic by Standard ICs and Programmable ROM Memories
12.1 STANDARD ICS FOR DESIGN IMPLEMENTATION
12.2 PROGRAMMING AND PROGRAMMABLE LOGIC MEMORIES (1/2)
12.2 PROGRAMMING AND PROGRAMMABLE LOGIC MEMORIES (2/2)
EXAMPLES (1/2)
EXAMPLES (2/2)
EXERCISES
QUESTIONS
Chapter 13: Implementation of Combinational Logic by Programmable Logic Devices
13.1 BASICS POINTS TO REMEMBER WHEN USING THE PLDS (PROMS, PALs, PLAs)
13.2 PAL (PROGRAMMABLE ARRAY LOGIC)
13.3 PLA (PROGRAMMABLE LOGIC ARRAYS)
EXAMPLES (1/2)
EXAMPLES (2/2)
EXERCISES
QUESTIONS
Chapter 14: Sequential Logic, Latches and Flip-Flops
14.1 FLIP FLOP AND LATCH
14.2 SR LATCH (SET-RESET LATCH) USING CROSS COUPLED NANDS
14.3 JK FLIP-FLOP
14.4 T FLIP-FLOP
14.5 D FLIP-FLOP AND LATCH
14.6 MASTER-SLAVE RS FLIP-FLOP
14.7 MASTER-SLAVE (PULSE TRIGGERED) JK FLIP-FLOP
14.8 CLOCK INPUTS
14.9 PULSE CLOCKING OF THE LATCHES IN THE FLIP-FLOPS
14.10 CHARACTERISTIC EQUATIONS FOR THE ANALYSISEXAMPLES
EXERCISES
QUESTIONS
Chapter 15: Sequential Circuits Analysis, State-Minimization, State Assignment and Circuit Implementation
15.1 GENERAL SEQUENTIAL CIRCUIT WITH A MEMORY SECTION AND COMBINATIONAL CIRCUITS AT THE INPUT AND OUTPUT STAGES
15.2 SYNCHRONOUS AND ASYNCHRONOUS SEQUENTIAL CIRCUITS
15.3 CLOCKED SEQUENTIAL CIRCUIT
15.4 CLASSIFICATION OF SEQUENTIAL CIRCUIT AS MOORE AND MEALY STATE MACHINE CIRCUITS
15.5 ANALYSIS PROCEDURE
15.6 CONDITIONS OF STATES EQUIVALENCY
15.7 IMPLEMENTATION PROCEDURE
EXAMPLES (1/3)
EXAMPLES (2/3)
EXAMPLES (3/3)
EXERCISES
QUESTIONS
Chapter 16: Sequential Circuits for Registers and Counters
16.1 REGISTERS
16.2 SHIFT REGISTERS
16.3 COUNTER
16.4 RIPPLE COUNTER (1/2)
16.4 RIPPLE COUNTER (2/2)
16.5 SYNCHRONOUS COUNTER
16.6 ASYNCHRONOUS CLEAR, PRESET AND LOAD (JAM) IN A COUNTER
16.7 SYNCHRONOUS CLEAR, PRESET AND LOAD FACILITIES IN A COUNTER
16.8 TIMING DIAGRAMS
EXAMPLES (1/3)
EXAMPLES (2/3)
EXAMPLES (3/3)
EXERCISES
QUESTIONS
Chapter 17: RAM, Address and Data Buses, Memory Decoding, Semiconductor Memories
17.1 DEFINITION OF RAM
17.2 TRISTATE OUTPUTS-CUM-TRISTATE INPUTS FOR A COMMON BUS ORGANIZATION OF THE BUFFER REGISTERS
17.3 COMMON BUS ORGANIZATION OF BYTES AT THE CELL ARRAYS IN RAM
17.4 INTERNAL ADDRESS DECODER IN A RAM
17.5 INTEGRATED CIRCUIT FOR A RAM
17.6 INTEGRATED CIRCUITS OF THE RAMS, ROMS AND OTHER DEVICES ON A COMMON SET OF CONTROL, ADDRESS AND DATA BUSES
17.7 EXTERNAL DECODING OF THE ADDRESS BUS TO THE INTEGRATED CIRCUITS OF A SYSTEM
17.8 SEMICONDUCTOR MEMORY
EXAMPLES (1/2)
EXAMPLES (2/2)
EXERCISES
QUESTIONS
Chapter 18: Fundamental Mode Sequential Circuits
18.1 GENERAL ASYNCHRONOUS SEQUENTIAL CIRCUIT
18.2 UNSTABLE CIRCUIT OPERATION
18.3 STABLE CIRCUIT ASYNCHRONOUS MODE OPERATION
18.4 FUNDAMENTAL MODE ASYNCHRONOUS CIRCUIT
18.5 ANALYSIS PROCEDURE (1/2)
18.5 ANALYSIS PROCEDURE (2/2)
18.6 RACES
18.7 RACE-FREE ASSIGNMENTS
EXAMPLES
EXERCISES
QUESTIONS
Chapter 19: Hazards and Pulse Mode Sequential Circuits
19.1 HAZARDS
19.2 IDENTIFYING STATIC HAZARDS
19.3 ELIMINATING STATIC HAZARDS
19.4 DYNAMIC HAZARDS
19.5 HAZARDS FREE CIRCUITS
19.6 ESSENTIAL HAZARDS
19.7 PULSE MODE SEQUENTIAL CIRCUIT
EXAMPLES
EXERCISES
QUESTIONS
Chapter 20: ADC, DAC and Analog-Digital Mix Interfaces
20.1 ANALOG TO DIGITAL CONVERTER (ADC OR A/D)
20.2 DIGITAL-TO-ANALOG CONVERSION (DAC OR D/A)
20.3 ANALOG/DIGITAL SWITCH
20.4 ANALOG MULTIPLEXER
20.5 ANALOG DEMULTIPLEXER20.6 INTERFACING LOGIC GATES WITH THE ANALOG CIRCUITS
20.7 EXEMPLARY DIGITAL ANALOG INTERFACING CIRCUITS
EXAMPLES
EXERCISES
QUESTIONS
Chapter 21: CPLDs and FPGAs
21.1 CPLDS
21.2 REGISTERED PAL
21.3 ARRAY LOGIC CELL
21.4 FIELD PROGRAMMABLE GATE ARRAYS (FPGAS)
EXAMPLES
EXERCISES
QUESTIONS
Index (1/2)
Index (2/2)

Content preview from Digital Systems: Principles and Design

514

Digital Systems

EXAMPLES

Give an example of fuse-links in an array logic for a CPLD.

Solution

A macrocell is at an output stage of a GAL. A macrocell in the exemplary array logic

GAL20V8 has the additional fuse/links. These are programmable like the fuse/links in

AND-OR arrays or PAL or PLA. The macrocell(s) of GAL are programmable by an external

programming unit, which fuses an undesired link to obtain the desired logic and/or sequen-

tial functions at the output stage(s). Example 21.6 describe interconnect link-method A pro-

gramming unit does the programming of the all the fuse/links present in the macrocells at all

the output stages as well as ...

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