October 2006
Intermediate to advanced
544 pages
20h 23m
English
Content preview from Digital Systems: Principles and Design
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323Sequential Logic, Latches and Flip-Flops
Cases in Sections 14.3.1.4 and 14.3.1.5 shows that when J = 1 and K = 1, the output of
JK flip flops toggles (changes to opposite state) on the clock edge.
A timing diagram depicts a state table of any flip-flop more clearly. Example 14.11 will
describe that.
Points to Remember
JK-flip flop has the following features:
When J = 1 and K = 1, the output of JK flip flops toggles (changes to opposite state) on
a clock edge.
When J = 0 and K = 0, the output of JK flip flops does not change on a clock edge.
When J = 0 and K = 1, the output Q resets to 0 after the clock edge.
When J = 1 and K = 0, the output Q sets to ...
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