Table 7.3 columns 3 and 5 gives fan-in for various families of gates. Fan-in for 74LS
family at 1 is 0.5 as i
source
(20 mA) is half of the value (40 mA) when a standard TTL is at the
input. Fan-in for LS family at 0 is 0.25 as i
sink
is one fourth (400 mA) from it compared to the
value (1600 mA) from a > 4 gate at the input. For CMOS 40 series gate fan-in at 1 as well
as 0 is only 0.025 as i
source
is (40 mA multiplied by 0.025 i.e. 1 mA), and i
sink
is (1600 mA
multiplied by 0.025 i.e. 40 mA).
We have learnt the concept of fan-out as the number of input next input stages, which
can be connected to a given type of a logic gate. Fan-out ...
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