Digital Systems: Principles and Design

308

Digital Systems

FIGURE 13.10 An implementation by 4 ´ 4 ´ 2 PLA with four dedicated and two feedback input variables, 4 ANDs and 2

ORs (l = 4, m = 2, n = 4).

Example 13.5

Show how will we design a hardware lock from an eight input variable PLA having eight

number 16 input AND gates to eight OR gates. Lock opens and generates output = 1 when

input variables are 10100111 and OR outputs Y

0

to Y

7

are as follows:

Y

0

= Sm(0, 12, 38, 89); Y

1

= Sm(10, 112, 138, 209); Y

2

= Sm(0, 12, 117, 133, 1769);

Y

3

= Sm(37, 49, 74, 189); Y

4

= Sm(53, 92, 108, 128); Y

5

= Sm(8); Y

6

= Sm(83, 1133);

Y

7

= Sm(1, 128, 138, 59); [Total 25 distinct minterms]

Solution

Maximum minterm ...