Parallel Computer Architecture

6.2 Base Design: Single-Level Caches with an Atomic

Bus

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instead first service the miss that caused it. This optimization imposes two require-

ments. First, it requires the machine to provide additional storage, a write-back

buffer,

where the block being replaced can be temporarily stored while the new block

is brought into the cache and before the bus can be reacquired for a second transac-

tion to complete the write back. Second, before the write back is completed, it is

possible that we will see a bus transaction containing the address of the block being

written back. In that case, the controller must supply the data from the write-bac