Parallel Computer Architecture

11.6 Precommunication in a Shared Address Space 877

available in modern processors, read latency can be hidden reasonably well even

under sequential consistency, at least on moderate-scale systems. Compiler schedul-

ing of instructions can help processors hide latency even better.

In general, conservative design choices—such as blocking reads or blocking

cac

hes—make preserving orders easier, but at the cost of performance. For example,

in dynamically scheduled processors, delaying the retirement of writes from the

reorder buffer until all previous instructions are complete to avoid rolling back on

writes (e.g., for precise exceptions) makes