September 1998
Intermediate to advanced
1056 pages
55h 28m
English
Content preview from Parallel Computer Architecture
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616
CHAPTER
8 Directory-Based Cache Coherence
Xbow I/O
CRAYIink network
SSD/SSR
Link-level protocol
adapter
Msg Ctrl
I/O translation
Invalidation
multicast
SSD/SSR
Link-level protocol
adapter
Msg Ctrl
Nl
Π
Tables
}*
Crossbar
K ££#
H
*ÜK*\
Ml
Directory
FIGURE 8.21 Layout of the Hub chip. The crossbar at the center connects the buffers
of the four different interfaces. Clockwise from the bottom left, the BTEs are the block
transfer engines. The top left corner is the I/O interface or II (the SSD and
SSR
translate
sig-
nals to and from the I/O ports). Next is the network interface (Nl), including the routing
tables. The bottom right is the memory/director ...
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