Parallel Computer Architecture

12.1 Technology and Architecture 951

DRAM bit array

- Memory bus

L

2$ J 128-byte blocks

-I—I-

Microprocessor chip interface

U $ J 32-byte blocks

Jp^pWord or double word

Processor

FIGURE 12.4 Bandwidths across a computer system. The processor datapath is sev-

eral words wide but typically has a couple word-wide interface to its

L<j

cache. The Lj cache

blocks are 32 or 64 bytes wide, but they are constrained between the processor word-at-a-

time operation and the microprocessor chip interface. The L

2

cache blocks are even wider,

but they are constrained between the microprocessor chip interface and the memory bus

interface, both width critical