Parallel Computer Architecture

1.1 Why Parallel Architecture 19

misses, which accounts for the zero-issue cycles. (Other studies ignore cache effects

or ignore pipeline latencies and thereby obtain more optimistic estimates.) We see

that, even with infinite machine resources, perfect branch prediction, and ideal

renaming, no more than four instructions issue in a cycle 90% of the time. Based on

this distribution, we can estimate the speedup obtained at various issue widths, as

shown in the right portion of the figure. Recent work (Lam and Wilson 1992; Sohi,

Breach, and Vijaykumar 1995) provides empirical evidence that to obtain signifi-

cantly larger amounts of parallelism ...