Parallel Computer Architecture

5.2 Memory Consistency 283

FIGURE 5,6 Partial order of memory operations for an execution with the write-

through invalidation protocol. Write bus transactions define a global sequence of

events between which individual processors read locations in program order. The execution

is consistent with any total order obtained by interleaving the processor orders within each

segment.

Answer A single processor will generate 30 million stores per second (0.15 stores per

instruction x

1

instruction per cycle x 1,000,000/200 cycles per second), so the total

write-through bandwidth is 240 MB of data per second per processor. Even ig-

noring address and othe ...