Parallel Computer Architecture

11.7 Multithreading in a Shared Address Space 901

IF1

IF2

RF

EX

DF1 DF2

WB

)fe(|>s(

X

M

54

m

FIGURE 11.26 Impact of late miss detection in a pipeline. Thread A is the current

thread running on the processor. A cache miss occurring on instruction A¡ from this thread

is only detected after the second data fetch stage (DF2) of the pipeline

(i.e.,

in the write-

back [WB] cycle of Afs traversal through the pipeline). At this point the following six

instructions from thread A (A

/+1

through A

¡+6

) are already in the different stages of the

assumed seven-stage pipeline (two cycles of instruction fetch [IF], one cycle of register fetch

[RF],

one cycl ...