Parallel Computer Architecture

1010 Index

MIPS (millions of instructions per

second), 230, 231, 257

MIPS R4000 processor, 910

MIPS R10000 processor, 597, 684,

868

misses. See cache misses

miss state holding registers (MSHRs),

924-925

access, 924

contents, 924

state entries, 925 (fig.)

MOESI protocol, 300

Monsoon, 494, 495, 496

MSI

write-back invalidation protocol,

293-299

bus read exclusive, 294

coherence satisfaction, 297

illustrated, 295 (fig.)

invalid state, 293

lower-level design choices,

298-299

modified state, 293

for processor transactions, 297

(fig.)

sequential consistency

satisfaction, 297-298

shared state, 293

state transitions, 294-296

transactions and, 293-29 ...