September 1998
Intermediate to advanced
1056 pages
55h 28m
English
Content preview from Parallel Computer Architecture
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652 CHAPTER 8 Directory-Based Cache Coherence
once the write has obtained ownership and even before invalidation acknowledg-
ments have returned. Atomic operations can also be implemented at the memory,
but it is easier to do this if we disallow the block from being cached in dirty state by
any processor. Then all writes go to memory, and the read-modify-write can be seri-
alized with respect to other writes as soon as it gets to memory. Memory can send a
response to the read component in parallel with sending out invalidations corre-
sponding to the write component.
Implementing LL-SC requires all the same consideration to avoid livelock as i ...
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