September 1998
Intermediate to advanced
1056 pages
55h 28m
English
Content preview from Parallel Computer Architecture
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926
CHAPTER
11 Latency Tolerance
state in the block (including a pending state with the SWB on), then it simply
returns it. Otherwise, it is placed in a pending read register that keeps track of it.
If the block accessed on a read or write is not in the cache (no tag match), then a
write back may be generated. The block is set to the invalid pending state, all SWBs
are turned off (except for the word being written if it is a write), and the appropriate
transaction is placed on the bus. If the tag does not match and the existing block is
already in pending state, then the processor stalls. Finally, when a response to an
outstanding request arrives ...
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