September 1998
Intermediate to advanced
1056 pages
55h 28m
English
Content preview from Parallel Computer Architecture
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296 CHAPTER 5 Shared Memory Multiprocessors
(let us continue to assume BusRdX), the block in the requesting cache transitions to
the modified state. Additional writes to the block while it is in the modified state
generate no additional bus transactions.
A replacement of a block from a cache logically demotes the block to invalid (not
present) by removing it from the cache. A replacement therefore causes the state
machines for two blocks to change states in that cache: the one being replaced
changes from its current state to invalid, and the one being brought in changes from
invalid (not present) to its new state. The latter state change canno ...
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