September 1998
Intermediate to advanced
1056 pages
55h 28m
English
Content preview from Parallel Computer Architecture
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398 CHAPTER 6 Snoop-Based Multiprocessor Design
Tags
Tags used mainly
by processor
Cached
data
Cached data
ί.
Ί
cache
Tags
L
2
cache
Tags used mainly
by bus snooper
FIGURE 6.7 Organization of two-level
snoopy caches. Only a single set of tags is
needed for each cache.
6.4 SPLIT-TRANSACTION BUS
An atomic bus limits the achievable bus bandwidth substantially, since the bus wires
are idle from the time when the address is taken off the bus until the memory system
or another cache supplies the data or response. In a split-transaction bus, transac-
tions that require a response are split into two independent subtransactions—a
request transaction an ...
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