September 1998
Intermediate to advanced
1056 pages
55h 28m
English
Content preview from Parallel Computer Architecture
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446 CHAPTER 6 Snoop-Based Multiprocessor Design
buses and data crossbars to scale to 64 processors. Each board consists of four 250-
MHz processors, four banks of memory (up to 1 GB each), and two independent
SBUS I/O buses. Sixteen of these boards are connected by a 16 x 16 data crossbar
with paths 144 bits wide as well as four address buses associated with the four banks
on each board. Collectively, this provides 12.6 GB/s of data bandwidth and a high
snoop rate of 250 MHz.
6.7 CONCLUDING REMARKS
The design issues that we have explored in this chapter are fundamental and will
remain important at moderate levels of parallelism. Of course, th ...
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