Parallel Computer Architecture

6.4 Split-Transaction

Bus

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Other than deadlock, a concern with these queue structures is maintaining

sequential consistency. With multilevel caches, it is all the more important that the

bus not wait for an invalidation to reach all the way up to the first-level cache and

return a reply; it should instead consider the write committed when it has been

placed on the bus and hence in the input queue to the lowest-level cache. The sepa-

ration of commitment and completion is even greater in this case. However, the

techniques discussed for single-level caches extend naturally to this case: we simply

apply them at each level of the cache hierarchy ...