Parallel Computer Architecture

8.7 Performance Parameters and Protocol Performance 645

MCUs. The case of remote transfers through processor reads and writes is limited

primarily by the limit on the number of outstanding memory operations from a pro-

cessor, which is not an issue for the DMA case. The DMA case has the additional

advantage that it requires only one bus transaction at the initiating end for each

memory block rather than two split-transaction pairs in the case of processor reads

and writes (once for the read and once for the write). At least in the absence of con-

tention across transfers, the local quad bus becomes a bandwidth bottleneck long

before the interconnectio ...