September 1998
Intermediate to advanced
1056 pages
55h 28m
English
Content preview from Parallel Computer Architecture
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916 CHAPTER 11 Latency Tolerance
provided in such processors. The EPC is fed by the PC chain, so it always contains
the address of the last instruction retired from the pipeline. When an exception
occurs, the loading of the EPC is stopped with the faulting instruction, all the
incomplete instructions in the pipeline are squashed, and the exception handler
address is put in the PC. When the exception handler returns, the EPC is loaded
into the PC so that the faulting instruction is reexecuted. This is exactly the func-
tionality we need for multiple contexts. We simply need to replicate the EPC regis-
ter, providing one per active context. Th
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