Parallel Computer Architecture

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CHAPTER

11 Latency Tolerance

(&variable), fetches the line in exclusive mode. The machine has a cache miss

latency of 32 cycles. Explicitly prefetch each needed variable (don't take into

account the cache block size). Assume that the cache is large (so you don't have to

worry about conflict misses) but not so large that you can prefetch everything at the

start. In other words, we are looking for just-in-time prefetching. The matrix

A [

i, j ] is stored in memory with

A [

i, j ] and

A [

i, j

+1 ]

contiguous. Assume

that the computation in the loop takes 8 cycles to complete.

11.16 Describe two examples in which a prefetching compiler's decisio ...