Parallel Computer Architecture

11.5 Proceeding Past Long-Latency Events 873

Performance Impact

Simulation studies have examined the extent to which hardware prefetching, specu-

lative read, and write buffering techniques can hide latency under different consis-

tency models. One study assuming an RC model finds that a substantial portion of

read latency can indeed be hidden using a dynamically scheduled processor with

speculative execution and that the amount of read latency that can be hidden

increases with the size of the reorder buffer even up to buffers as large as 64 to 128

entries (Gharachorloo, Gupta, and Hennessy 1992). A detailed study compares the

performance of